1. Field of the Invention
The present invention relates to a layout structure for a CMOS circuit, and particularly to a layout structure for a CMOS circuit which allows easy delay adjustment.
2. Description of the Related Art
In conventional CMOS circuits, timing adjustment is conducted at various points. For example, a delay circuit having an adjusted delay value is used for pulse width adjustment in chopping a clock signal to pulsate. FIG. 5 is a timing chart showing operations of the pulse width adjustment. A pulse signal (CK) denoted at (a) in FIG. 5 is delayed and inverted as indicated by (b). From the result of this and the original circuit, NAND is obtained so that a pulse as denoted at (c) can be obtained with a pulse width equal to a delay value. In this case, if the pulse width is too large, racing occurs on a path from the master output of a latch. Otherwise, if the pulse width is too small, no value may be latched or a delay value to a slave output may have an error.
Other examples are delay adjustment for restricting racing within a range in which no over-delay occur and clock phase adjustment for adapting flexibly an inter-cycle period to fit a data transfer velocity.
Although these adjustments are adopted in design stages, it often appears that designed adjustment values cannot be achieved in frequent cases due to problems of immature manufacturing processes or various calculation errors. In those cases, actual chips are fed back and subjected to measurements to specify the reasons. Thus, manufacturing data, e.g., the layout structure of the chips is modified, and the chips are remanufactured so that the designed adjustment values can be achieved.
With respect to layout structures of CMOS circuits, various techniques are known conventionally (for example, see Patent Literature 1: Japanese Patent Laid-Open No. 62-277747).
In such a modification of a layout structure in the prior art, widths and lengths of transistors are adjusted in general cases. For this purpose, the layout structure has to be modified totally throughout a diffusion layer (transistor layer), a resistor layer, and a metal layer (metal wire layer), and so requires a very long time and huge costs.
Meanwhile, if the modification of the layout structure can be achieved with a modification only to the metal layer as an upper layer, the layout structure adopted in chips being manufactured can be partially reflected directly on the lower layers such as resistor and diffusion layers below the metal layer. Then, not only the turn-around time can be reduced but also the costs required for manufacturing masks can be saved.
The present invention has been made to solve these conventional problems and has an object of providing a layout structure for a CMOS circuit in which a modification for delay adjustment to the layout structure of the CMOS circuit can be achieved by modifying only a metal layer as an upper layer, so that turn-around time can be reduced and mask manufacturing costs can be saved.